Physical Design & DFT

Increasing complexity and integration, shrinking geometries and consequent physical effects have been some of the ongoing challenges GDA's ultra deep sub micron flow has had to address. First-pass silicon is a critical requirement our partners are increasingly relying on to tackle an ever-shrinking product window and faster design obsolescence.

The team at GDA has delivered on integration of complex multimillion gate SoC designs with multiple voltage islands and multiple clock domains in nanometer technology using hierarchical place and route. All this has been accomplished while also addressing the challenges of Signal Integrity (SI) and Ultra Deep-Sub-Micron effects. Further, the team has the execution expertise on issues related to the physical effects that affect reliability and manufacturability such as Crosstalk, static and dynamic IR drop, electron migration, and antenna effects at length.

GDA provides the following services for Physical Design:

  • Floor and power planning
  • Placement and routing
  • Power and timing analysis
  • Clock tree synthesis
  • Skew minimization
  • Signal integrity (IR & EM) fix and analysis
  • Formal verification
  • Static timing analysis (STA)
  • DFM – redundant vias, metal density
  • Layout – chip finishing
  • Physical verification – DRC/LVS/ERC/PAE

DFT Services

Product structures and the chips that go inside them are becoming increasingly complex. So, it is ever more important to identify non–functional parts very early in the product life cycle to avoid cost overruns due to de-bug support.

The tests for identifying such parts are conducted in two phases: the wafer test and the final test after assembly.

GDA provides the following services for design for test (DFT):

  • Scan chain insertion
  • Memory BIST insertion
  • Boundary scan insertion
  • icBIST implementation
  • ATPG vector generation
  • Test vector simulation
  • Test vector fault coverage analysis
  • Library development
  • Customers