SoC/ASIC & Verification


GDA’s engineering and design team has taped out in excess of 50 ASIC designs with varied levels of complexity and integration. Several ASIC designs were implemented on 90nm technology node with gate counts going up to 18 million and clock domains running up to 700 MHz.

GDA has developed Cadence, Synopsys, and Magma design flows, all of which have been deployed successfully to reach close to 100% first-pass silicon success.

Our offerings in this area include:

  • System level modeling, Planning and Specification
  • IP integration
  • Micro-architecture and design specification
  • RTL Design and Verification
  • Property checking, model checking and assertions
  • System and RTL co-simulation
  • Synthesis and STA
  • Gate level Verification
  • Front and Back end Design For Test (DFT ) Services
  • Floor Planning, Power planning, Place & Route, and Timing Closure
  • Formal Verification and Equivalency Checking
  • Physical verification and tape out.

Design verification services include:

  • Test Strategy and Plan
  • Architecting Verification Environment
  • Verification IP strategy
  • System level and RTL co-simulation
  • Test case development
  • Regression Automation and Distribution
  • Customers